The physical implementation of IC designs developed using Hardware Description Languages (HDL), such as Verilog and VHDL, is a tedious, effort and time-intensive process. The main IC design development steps are typically high-level architecture definition, RTL code development, functional verification, synthesis and timing optimization, floor planning, cell placement and timing optimization, routing and final verification. If a design is unable to meet design timing or successfully complete routing in the planned floor plan or block area, then it is considered a physical implementation failure. Physical implementation failures are found late in the development cycle. In advanced technology processes such as 40 nm and below, the larger design sizes and smaller geometries exacerbate the risk of physical implementation failure. This creates a significant time and development cost risk for a design team.
The design team attempts to resolve physical implementation issues with a combination of methods: (i) decrease the design utilization, i.e. implement the block with larger silicon area; (ii) change the floor plan to allocate more area for the affected block, often causing a sub-optimal floor plan and degradation in design performance; and (iii) change the design itself by changing the design's HDL description. Each of the methods creates a significant loss in terms of increased time to design implementation completion, time to market for the finished product, larger silicon area, reduced performance and clock frequency, risk of not fitting into chosen chip package, and higher development cost.
Given the high cost of resolving physical implementation issues, a method to predict such issues at the pre-floorplan stage of design development is very valuable to design development teams. By predicting such issues early in the development cycle, the development team can take corrective steps before going to physical implementation, and hence significantly reduce risk to timely completion and overall cost of development.
Existing electronic design automation (EDA) tools try to detect physical implementation issues by applying checking-rules to each of the objects in the design. The checking rules look for high fan-in, high fan-out, large multiplexors and other properties. EDA systems attempt to identify timing critical paths.
Existing EDA tools do not consider the interactions of the detected physical implementation issues. A critical timing path issue might normally indicate placing and routing instances close together. A routing congestion issue might normally indicate spreading out the layout. If both issues are present in close proximity the risk of a physical implementation failure is greatly increased.